Characterisation of Ultra-Small Pocket Si0.7Ge0.3 Junction-less Tunnel FET with SOI

The Tunnel FET has substantial potential to overcome limitations imposed due the scaling in low voltage region because of its steep subthreshold slope relative to its corresponding junction based MOSFET counterpart. Use of Si
_0.7
Ge
_0.3
material as pocket region (0.5nm) enhances band-to-band tunneling by decreasing tunneling distance. The proposed pocket ultra small pocket Si
_0.7
Ge
_0.3
Junction-less TFET(JLTFET) exploits advantage junction-less regions and p-type pocket region to improve device performance in subthreshold region showing improvement in subthreshold slope and better ON and OFF-state drain current ratio as compared to other similar TFET structures. Proposed ultra small pocket JLTFET shows high value ION/IOFF ratio and good subthreshold behaviour even with 2nm gate length and body thickness 0.5nm. All the designs proposed for n JLTFETs are designed on visual TCAD 2D/3D device simulator.