m-dimensional DT-CNN implementation via nested lower dimensional architecture

The development of the cellular neural network (CNN) paradigm, and its wide use in many application fields, has shown that CNN is a complementary, and in some cases alternative, approach to classical computing machines. Despite their theoretical success, CNN VLSI implementations still suffer from size and dimension limitations. In fact, while the biggest CNN chips, due to VLSI constraints and to planar technology, have no more than few thousands of cells arranged on a 2D array, real problems may require millions of cells and may be multidimensional. We focus on the implementation of an m-dimensional DT-CNN with a limited number of lower (m-i)-dimensional DT-CNN circuits. As the target dimension is (m-i), we choose i=m-2 or i=m-1. In order to obtain an architecture using 2D or ID DT-CNN circuits which were proven to be feasible.