Verification of logic control design using SIPN and model checking: methods and case study

This paper deals with the verification of logic control system designs by signal interpreted Petri net (SIPN), which is a special extension of an ordinary Petri net (PN) by input and output signals. Such extensions provide more power for a specification. However, due to the extensions the basic Petri net analysis method is not strong enough to determine the properties. A model checking approach has been applied to the verification of an SIPN design. The requirements to be verified are expressed in temporal logic (TL). Via a model checking algorithm the validity of such requirements can be checked automatically in every possible input sequences. In an error case a sequence of states is calculated, which indicates a trace leading to the violation of the requirements. A case study has shown that this approach can effectively locate errors in the design process.