An integrated circuit for the in situ characterization of CMOS best-process micromachining

We have developed an integrated circuit for in situ monitoring and characterization of CMOS post-process micromachining. In our demonstration, the circuit provides automated readout of N-well resistors surrounding each of 140 micromachining test structures at up to 14,000 samples per second per device during the post-process silicon etch. We use this circuit to examine the effect of pit size, surrounding thin film layers, and topography in a 2 /spl mu/m CMOS process with a XeF/sub 2/ post-process step, although the circuit and results are of use to EDP, TMAH, and plasma post-processing.