Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane

As stated in the introductory section, DDR signaling has evolved tremendously over the last two decades, leading to diversification not only in the architecture of the memory array but also in that of the interface. Application-specific channels have influenced the I/O design nearly as much as system power and bandwidth requirements have. The growing impact of the multidrop server channel, along with a broad range of target environments, has led the DDR branch to incorporate multitap DFE, while shrinking supply voltages to facilitate low-power operation led LPDDR to completely rethink the output driver structure. At the same time, GDDR has reached speeds requiring nearly equal care of the external channel and the chip itself. With all these adaptations and many others not captured here, the broader DDR family looks to continue to push the boundaries of single ended signaling into the future. For additional details, see the perspective on the DRAM interface.