Challenges for atomic scale modeling in alternative gate stack engineering

We review the challenges for atomic scale modeling of alternative gate dielectric stacks. We begin by highlighting recent achievements of state-of-the-art atomistic simulations of the Si-SiO/sub 2/ system, showing how such calculations have elucidated the microscopic origins of several important experimental phenomena. For the benefit of readers who may be unfamiliar with the simulation tools, we overview and compare the relevant methods. We then describe the difficulties encountered in extending these approaches to investigate high-k dielectric stacks, pointing out exciting research directions aimed at overcoming these challenges. We conclude by presenting a roadmap of computational goals for atomic scale modeling of alternative gate dielectrics.