A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution

In order to obtain higher performance of digital circuits in advanced technology nodes, the effects of delay variability on performance should be reduced as much as possible with less overheads. Clock scheduling and speculative execution have potential to ease the influence of the delay difference among signal paths and the delay variability in each signal path, respectively. In this paper, we propose a high-performance digital circuit design method with speculative executions with less overhead by utilizing clock scheduling with delay insertions effectively. The necessity of speculations that cause overheads is effectively reduced by clock scheduling with delay insertion. Experiments show that a generated circuit achieves 26% performance improvement with 1.3% area overhead compared to a circuit without clock scheduling and without speculative execution.