A 20 Gb/s 3.8 pJ/bit 1:4 Demux in 45-nm CMOS

This paper presents the design and characterization of a low power 20 Gb/s 1:4 demultiplexer (Demux) in 45-nm SOI CMOS. For the design of the latch, which is used primarily inside the key building blocks of the 1:4 Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Demux, are presented. The designed 1:4 Demux uses a supply voltage of 1 V, dissipates a total of 77 mW of power, and occupies an active area of 0.122mm². Among the reported inductorless CMOS 20 Gb/s 1:4 Demuxes, the presented Demux achieves the best energy figure of 3.8 pJ/bit.