VHDL-based digital circuit synthesis: a case study

Present day computer-aided design of VLSI circuits calls for specifying the design at a sufficiently high level of abstraction. This approach allows the designers to describe systems in terms of a set of interacting components, which facilitates the reuse of subsystems in a complex design and reduces the design cycle. This paper describes a case study of the Description-and-Synthesis methodology for digital circuit design. Distinct digital addition algorithms were coded in VHDL and automatically synthesized using two different commercial Electronic Design Automation (EDA) environments. The resulting circuits were simulated and the overall results are shown and discussed.