Device robust-design using multiple-response optimization technique

A test device of NMOS is obtained by using TCAD simulation tools with the critical electrical parameters being optimized simultaneously with respect to device operability, reliability, and power consumption. A novel optimization technique that expands the application of conventional design-of-experiments (DOE) technique such as the Taguchi Method, into the area of multiple-response problems, is preposed to aid the design of such a robust device. The simulation data of a 0.25 /spl mu/m NMOS device are used to illustrate the implementation of this method.