Circuit design challenges for high-speed CMOS continuous-time switched-current /spl Sigma//spl Delta/ modulators

This paper discusses circuit design problems when implementing low-pass CMOS continuous-time switched-current /spl Sigma//spl Delta/ modulators for high-speed operation or wide-bandwidth conversion. These problems cause difficulties when certain high-performance architectures are intended to be used for improving performance, such as multi-bit quantizer, cascade structure, high-order single loop structure, and parallelism. These problems arise mainly as a result of an uncertain transfer function, an extra loop delay, and/or mismatching among integrator capacitors of the modulator. These problems will be discussed to explore the limitation when more advanced architectures are applied.