Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic CMOS circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of the circuits by as much as 50%.