Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node Nanosheet FETs

Sub-7-nm node nanosheet field-effect transistors adopting metal source/drain (S/D) structure were analyzed in depth using fully calibrated TCAD. Metal S/D structure was formed by anisotropic etching of low-k and S/D epi regions followed by metal-line (M0) deposition without additional mask under conventional CMOS process. Larger S/D metal depth increases the contact area between S/D epi and M0, thus increasing current drivability greatly without decreasing contact resistivity. A slight ac performance loss was due to the increase in intrinsic capacitance by the improved drivability. Tensile stress of M0 induces compressive stresses vertical to the channel and tensile stresses along the channel, which reduces and improves dc performances further for p-and n-type devices, respectively. Although the stress in the channel direction decreases by the recessed S/D epi, significant reduction of contact resistance compensates the reduced stress effects and improves RC delay consequently. Greatly recessed S/D epi increases the performance variations due to the channel stress variations as the open critical dimension (CD) varies. But when the open CD is tightly controlled by the latest technology such as extreme ultraviolet radiation, the metal S/D structure is competitive to achieve superior dc/ac performance under device scaling in sub-7-nm node and below.