Phase-Disposition PWM Based 2DoF-Interleaving Scheme for Minimizing High Frequency ZSCC in Modular Parallel Three-Level Converters

This paper proposes a two-degree-of-freedom (2DoF) interleaving scheme based on phase-disposition (PD) PWM for minimizing the high-frequency zero-sequence circulating current (ZSCC) in modular interleaved three-level converters. The method incorporates an internal interleaving by phase-shifting the carriers in each individual converter, and an external interleaving by phase-shifting the carriers of the different converters. A general harmonic distribution analysis which is valid for all types of voltage source converters is carried out to simplify the evaluation of the proposed method. A comprehensive evaluation of the proposed method shows that the PD-2DoF interleaving scheme produces the lowest ZSCC maximum value as compared to existing approaches. Moreover, it can achieve comparable performances as existing methods do in terms of output quality and common mode voltage magnitude, showing a great potential for practical implementation. Simulation and experimental results are obtained to demonstrate the performance of the proposed method. Generalization of the 2DoF interleaving scheme to high-level converter is also discussed in this paper.