Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors

To alleviate the hardware complexity of pipelined parallel multiple-input multiple-output (MIMO) detectors, this paper proposes an optimized architecture for interference cancellation units (ICUs). The tree structure and the critical path of the detector are first analyzed to gather information for the optimization. Based on the information, the dataflow in a pipeline stage is parallelized, and the adders in ICUs are clustered into removable nodes without elongating the critical path. By adopting the proposed architecture instead of its conventional counterpart, about 3.5 times more adders can be evicted from the detector for various MIMO configurations. A prototype MIMO detector that processes 7.15 Gbps while consuming 39.9 pJ/b is implemented to confirm that the architecture is indeed effective in mitigating the complexity.