Tradeoff between interconnect capacitance and RC delay variations induced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed.