Real time radar target detection under jamming conditions using wavelet transform on FPGA device

An architecture and a prototype implementation of radar target detection under jamming condition are presented. This paper presents an implementation based on the field programmable gate array (FPGA). The algorithm designed in this paper is based on multiresolution wavelet analysis, calculation of the wavelet maxima coefficients, integration of the maxima coefficients and identification of the target pulse edges from unwanted coefficients. The implementation occupies about 2500 configurable logic blocks on a Xilinx XC4000XLA family FPGA.