ML-Assisted DVFS-Aware HEVC Motion Estimation Design Scheme for Mobile APSoC

High-efficiency video coding (HEVC) is the latest video standard, and a variety of HEVC chips are being incorporated into the application processor system-on-a-chip (APSoC) within mobile devices. However, the coding bandwidth accessed for the motion estimation (ME) operation within HEVC has changed over time because of the adoption of the intelligent power management mechanism within the APSoC. To achieve a low-power high-performance HEVC design, the on-demand coding bandwidth must be considered in the design. In this paper, we develop an intelligent dynamic voltage-frequency-scaling-aware (DVFS-aware) coding-bandwidth-efficient HEVC ME controller algorithm model. We also develop a low-power high-performance VLSI hardware architecture by joining a machine learning (ML) scheme and a convex optimization (CO) method that is adaptive to the time-altering coding bandwidth. The proposed HEVC ME controller design can be integrated into ME to realize a coding bandwidth, coding bit rate, and coding-quality-optimized HEVC ME design for mobile APSoC, therein utilizing an intelligent power management mechanism. The experimental results show the effectiveness of the power and performance of the proposed design.