Performance optimization for high-order continuous-time /spl Sigma//spl Delta/ modulators with extra loop delay

Extra loop delay in a continuous-time modulator can cause a stability problem, especially when the modulator uses a high-order single-loop architecture and operates at a high sampling rate. This paper investigates the impact of extra loop delay on the performance of high-order (single-loop) modulators. A solution to compensate this delay and thereby optimize performance is proposed in this paper. The circuit architecture for this solution is also presented to facilitate a practical realization.