Optimizing the number of parallel channels and the stage resolution in time interleaved pipeline A/D converters

In this paper the effect of the number of parallel channels and the stage resolution on the sample rate and power dissipation of time interleaved parallel pipeline analog-to-digital converters (ADC's) with identical stages are examined. Simple formulas are given to determine an optimum number of parallel channels and stage resolution for a given technology with respect to the conversion rate and current consumption. The formulas are applied for to 10 bit pipeline ADC using a standard 0.5 /spl mu/m CMOS process parameters.