Area-time efficient serial-serial multipliers

A new serial-serial multiplier is being proposed which requires only N/2 conventional cells for multiplying two N-bit numbers, compared to N cells needed in existing structures. The significant aspect of the new design is that this 50% reduction in hardware has been achieved without degrading the speed performance. This is achieved by exploiting the fact that some cells are idle for most of the multiplication operation. In the new design, the computations of these cells are re-mapped to other cells, which makes them redundant. The proposed architecture is the first bit serial-serial structure with a comparable area-time performance to the bit serial-parallel structures. Furthermore, the proposed structure is superior in area-time performance to all existing serial-serial realisations.