A DLL based 10-320 MHz clock synchronizer

A clock synchronization scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analog and digital DLLs to align phases of two different frequency clocks. Simulation results represent that the internal clock is synchronized to the reference clock by tracking the dual feedback loop. The whole circuit design was performed using 0.35 /spl mu/m CMOS technology. Power dissipation is about 42 mW at 320 MHz with a single 3.3 V supply.