Generation of accurate on-chip time-constants using a monolithic CMOS PLL with hybrid analog and digital control

A method for generating on-chip time-constants with accuracy limited by that of on-chip capacitors is presented. The technique uses an adjustable constant-g/sub m/ bias-circuit along with a fully-integrated charge-pump CMOS PLL with a free-running frequency of 250 MHz. The VCO is composed of an adjustable constant-g/sub m/ bias circuit, which controls a g/sub m/-controlled oscillator. The PLL is used to lock the VCO to a crystal reference, which causes the bias circuit to generate a certain well-known transconductance. The bias circuit then biases circuits with well-defined time-constants, since they are inversely proportional to transistor transconductances. The design has been fabricated in a 0.35 /spl mu/m CMOS process, using an area of 1600/spl times/1600 /spl mu/m/sup 2/.