Substrate current protection in smart power IC's

In this paper, we describe and characterize a parasitic current, called substrate current injection in a SMART POWER technology. This parasitic current occurs when a normally reversed bias diode becomes forward biased and can disrupt the normal IC's functionality. We propose two design solutions able to decrease this parasitic current influence. These solutions, based on 2D simulation and on real-size measurements, are fully compatible with a standard technological process. The first one, consists in a correct guard ring polarization, in this case we can divide by 3 the injected current. The second one, based upon a special alignment for the N buried layer can decrease the parasitic current by a factor of 10.