A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 /spl mu/m CMOS

This paper describes a 1.6 GHz clock synthesizer which employs a delay locked loop (DLL) to generate multiple phases that are combined to produce the desired output clock frequency. A self correcting circuit ensures that the DLL arrives at the correct locked state irrespective of its power-up state or following either a wide variation in the input reference clock frequency or missing pulses in this clock signal. The measured edge peak-to-peak and r.m.s. jitter for a 1.6 GHz output clock was 20 ps and 3.1 ps respectively. The circuit is powered from a 3.3 V supply and was fabricated on a 0.5 /spl mu/m generic digital CMOS process.