An 8-bit 125 MS/s CMOS folding ADC for Gigabit Ethernet LSI

An 8-bit 125 MS/s CMOS folding ADC using an equalizing technique is presented, which reduces the settling time of the analog folding processor to obtain a higher sampling rate. The prototype chip, fabricated in a 0.35 /spl mu/m triple metal digital CMOS process, occupies an area of 0.8 mm/sup 2/ and consumes 110 mW achieving 6.4 effective bits for a Nyquist input signal.