A highly versatile 0.18 /spl mu/m CMOS technology with dense embedded SRAM

Summary form only given. We report on a 3.3 V/2.5 V compatible, 1.5 V high performance dense CMOS SRAM technology utilizing a 2.74 um/sup 2/ 6-T bitcell. This 0.18 /spl mu/m CMOS process with a nominal 0.13 /spl mu/m gate poly and a 30 /spl Aring/ gate oxide utilizes aggressive interwell isolation, enhanced self-aligned local interconnect, low-K interlevel dielectric, and scaled copper metallization. In addition, the technology allows for low leakage, high density and SER resistant embedded SRAM applications by allowing integration of low leakage array transistors, buried channel pMOS loads, self-aligned contacts and triple well in the memory array. Finally, this integration includes a 70 /spl Aring//30 /spl Aring/ DGO technology for 3.3 V interfaces. High performance 6-T bitcell operation, 8 Mb stand-alone SRAM yield and high performance DSP circuit with 4 Mb embedded memory with this aggressively scaled bitcell has been successfully demonstrated. Cell currents of 85 /spl mu/A has been achieved for a supply voltage of 1.5 V while maintaining static noise margin in excess of 220 mV.