A 10-bit, 3 V, 100 MS/s pipelined ADC

The design of a low-power 10-bit, 100 MS/s ADC is presented. The ADC is based on a pipelined architecture in which the number of bits converted per stage and the stage sizes were optimized to simultaneously achieve the desired linearity while minimizing the total power. When operated at 100 MS/s with a 3 V supply the ADC core dissipates 105 mW. The ADC was fabricated in a 0.35 /spl mu/m double poly CMOS process.