An 82–107.6-GHz Integer- $N$ ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta–Sigma TDC

A W-band integer-N all-digital phase-locked loop (ADPLL) aiming for wide frequency tuning range (TR) and low phase noise is proposed. The W-band ADPLL employs a digitally controlled oscillator (DCO) with split transformer and dual-path exponentially scaled switched-capacitor ladder and a clock-skew-sampling delta-sigma time-to-digital converter (TDC). The 65-nm CMOS W-band ADPLL measures a frequency TR of 27% from 82 to 107.6 GHz and phase noise from -106 to -110 dBc/Hz at 10-MHz offset and -84 to -87 dBc/Hz at 100-kHz offset while consuming 35.5 mW and occupying a 0.36 mm
²
core area, corresponding to a figure of merit (FOM) of -171 ~ -173 dB and FOMT of -178 ~ -181 dB.