Applying placement-based synthesis for on-time system-on-a-chip design

This paper examines the fundamental issues in timing closure, using present-day methodologies, for designs enabled by System-on-a-Chip (SOC) silicon technologies. Placement-based synthesis is proposed as a method to address these issues, and its benefits are contrasted against the problems of current methods. Finally, this paper discusses application of placement-based synthesis for optimum benefit in enabling on-schedule SOC design.