Analysis of CMOS-compatible lateral insulated base transistors

The authors describe the performance of various lateral insulated base transistors (LIBTs) fabricated with a 2.5- mu m digital CMOS-compatible high-voltage integrated circuit (HVIC) process. Structural modifications have been proposed to the LIBTs reported to date, in order to improve their on-stage performance. The modifications have been achieved with the use of charge-controlled n/sup +/ buried layers incorporated within the device structures. These LIBTs are implemented with a novel HVIC process which is based on a 2.5- mu m digital CMOS fabrication sequence. This process utilizes three additional steps carried out prior to the CMOS fabrication sequence. An important feature of this HVIC process is the use of a 400-AA gate oxide, which makes the power devices, fully compatible with the low-voltage digital circuits. During this work, a specific on-resistance of 0.016 Omega -cm/sup 2/ and a turn-off delay of 90 ns have been obtained in an improved LIBT structure which is capable of withstanding up to 250 V.<
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