Analysis of temperature effects on maximum power-efficiency of pass transistor logic networks in low-voltage CMOS

This paper presents a comprehensive analysis of the effects of increased temperature on maximum power-efficiency (powerd-delay-product) of pass-transistor networks operating at low supply voltages using deep-submicron CMOS technology. Numerous gate functions, such as OR, NOR, AND, NAND, XOR and XNOR have been designed in double pass-transistor logic (DPL) and swing-restored pass-transistor logic (SRPL). These circuits have been investigated under various operating conditions: fanin, fanout, power supply voltage and temperature. The results show that increased temperature significantly affects the maximum power-efficiency operating point of these logic gates and consequently, the optimum operating point.