Comparative Study on Charge Trapping Induced ${V}_{\textsf{th}}$ Shift for GaN-Based MOS-HEMTs With and Without Thermal Annealing Treatment

In this paper, threshold voltage (
${V}_{{\textsf {th}}}$
) shift in Al
₂
O
₃
/ AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) induced by charge trapping and the impacts of postmetallization annealing (PMA) were studied. In addition to the transient voltage shift caused by interface trapping effect, retentive voltage shift was also observed which was attributed to border traps with very large emission time constant (
$\tau _{e}$
). PMA has little influence on the transient
${V}_{\textsf {th}}$
shift which is related to interface traps with
$\textsf {18}~\textsf {s}< \tau _{e}< \textsf {54}$
s, while the total interface traps with
$\textsf {4}~\textsf {s} < \tau _{e}< \textsf {54}$
s are reduced by PMA from
$\textsf {4.03} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$
to
$\textsf {1.77} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$
. Interface trapping dominates at low program voltage (
${V}_{p}$
), while border trapping becomes remarkable with
${V}_{p}$
above the critical level. Due to the cumulative border trapping effect, an increase in program voltage by per volt causes an additional retentive voltage shift by about
$\textsf {1}$
V. PMA leads to an increase in critical
${V}_{p}$
from 5 to 7 V, which therefore results in a decrease in the density of total accessible border traps from
$\textsf {1.99} \times \textsf {10}^{\textsf {13}}\,\,\textsf {cm}^{-\textsf {2}}$
to
$9.25\times \textsf {10}^{\textsf {12}}$
cm
⁻²
with
${V}_{p}$
up to 12 V. The border trapping for both devices with and without PMA shows similar retention characteristics, with
${V}_{{\textsf {th}}}$
recovery as small as 1.2 V after one week.