CMOS high speed interpolators based on parallel architecture

In our project, we design a series of interpolators, including twice, four-time and eight-time data interpolators. In our design, we adopt the parallel architecture to realize the circuits to make the speed of twice (/spl times/2), four-time (/spl times/4) and eight-time interpolators reach about 50, 40 and 30 MHz respectively. We use 0.8 /spl mu/m double-metal single poly CMOS technology to fabricate our chips. To balance speed and accuracy of the interpolators, we use an eighth-order sine function as the interpolation function, and utilize the symmetry of sine function to simplify the structure of interpolator. The interpolating error is about 1.5%. The operating power voltage is 5 V and power dissipation is 70 mW at 50 MHz. The chips of our design are suitable for high speed digital signal processing, image processing and other applications.