On the scheduling algorithm of the dynamically trace scheduled VLIW architecture

In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hardware. These VLIW instructions are cached so that the machine can spend most of its time executing VLIW instructions without sacrificing any binary compatibility. This paper evaluates the effectiveness of the DTSVLIW instruction-scheduling algorithm by comparing it with the first come first served (FCFS) algorithm, used for microinstruction compaction, and the greedy algorithm, used by the Dynamic Instruction Formatting (DIF) architecture. We also present comparisons between the DTSVLIW, pure VLIW, and the Power PC620 processor. Our results show that the DTSVLIW scheduling algorithm has almost the same performance as the Greedy and FCFS. The results also show that the DTSVLIW performs better than the DIF for important machine configurations, better than pure VLIW implementations in most cases, and better than the Power PC620 using equivalent hardware resources.