Design and performances of a compensated mean timer

An integrated mean timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8 /spl mu/m integrates input and output ECL translators. The drift cancellation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external control voltage can be used. The circuit can also run without any cancellation system. In the last part, a sub-delay resolution system is discussed.