Self-checking circuits versus realistic faults in very deep submicron

IC technologies are approaching the ultimate limits of silicon in terms of device size, power supply levels and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise as well as to small manufacturing defects that may result in spurious faults. Such faults are difficult to (or can not) be detected by manufacturing testing and will result in unacceptable rates of errors in the field. Self-checking design can be used to cope with this problem, but usually it addresses logic faults. This paper analyzes the behavior of self-checking circuits under various spurious faults likely to occur in very deep submicron technologies.