TSV Transistor—Vertical Metal Gate FET Inside a Through Silicon VIA

A new vertical field-effect transistor (FET) has been fabricated inside a through silicon VIA (TSV). Front side and backside of a 200-
$\mu \text{m}$
-thin p-doped Si wafer were highly n-doped to shape the source/drain areas of the FET. The lateral surface of the TSV forms the channel with a length of
$200~\mu \text{m}$
(wafer thickness) and a width of
$63~\mu \text{m}$
(circumference of the 20-
$\mu \text{m}$
hole). A stack of SiO
₂
and Al
₂
O
₃
was used as gate dielectric material and Ru/TaN/Ru was deposited as gate metal using atomic layer deposition. The n-channel TSVFETs showed saturation currents of 150
$\mu \text{A}$
for a gate voltage of 4 V and an ON/OFF current ratio of about 10
⁴
.