Testing The Limits of TaN Barrier Scaling

Continued scaling dimensions of interconnects used for Si chip integration reduces the available cross sectional area for conduction. As Cu requires a protective diffusion barrier, TaN and a liner such as Co or Ru is frequently chosen to fulfill the various requirements such as time dependent dielectric breakdown (TDDB). Due to the higher resistivity, scaling the barrier/ liner thickness with the line dimension is desirable, but has proven difficult much below 2nm. One aspect here is the limited conformality when using physical vapor deposition (PVD) as the method of choice. Conformal methods such as atomic layer deposition (ALD) have been studied extensively as well for this application. In this paper, we investigate the limits of PVD TaN thickness scaling while maintaining Cu diffusion barrier properties. For this purpose, a planar metal-insulator capacitor has been employed for TDDB testing which was specifically designed to avoid any process related damage to the low-k dielectric. The TaN range examined here was between 0.2 to 3nm, deposited by a PVD process with low input power in order to control deposition accurately below 1nm thickness. It is found that both Co and Ru can add significantly to the TaN barrier integrity. The results further suggest that TaN can be thinned to less than 0.8nm and yet maintain barrier integrity. In particular the combination of TaN and Ru was found to show excellent barrier properties, with TaN as thin as 0.5nm. The impact on line and via resistance between 12 and 24nm wide is being discussed.