Mechanism and Resolution of Implant Induced Electrical Discharge Damage in GaAs IC

Electrical discharge damage is an unpredictable source of yield loss and a constant challenge to device reliability for the micro-electronics industry. There is considerable history and established methodology for handling charging effects for the silicon semiconductor sector, but literature is generally limited for GaAs and III-V compound semiconductor manufacturing. In this paper, electrical charging and subsequent discharge defects created during isolation implant processing of epitaxial wafers combining hetero-junction bipolar transistor and HEMT are discussed. As is common in semiconductor fabrication, a combination of the circuit layout, process sequence and tool configuration formed the ideal condition for a surge of electrical charging related yield failures. Through extensive examination and analysis, the primary source and mechanism of the failure were identified. These findings lead to development of proper detection and the resolution of the issue through key process improvements that ultimately enhanced yield and the GaAs integrated circuit die robustness against charging induced damage.