Impact of electron and hole inversion-layer capacitance on low voltage operation of scaled n- and p-MOSFET's

The influence of inversion-layer capacitance (C/sub inv/) on supply voltage (V/sub dd/) of n- and p-MOSFET's is quantitatively examined. The physical origin of the effect of C/sub inv/ on V/sub dd/ consists in the band bending of a Si substrate in the inversion condition due to C/sub inv/, which is not scaled with a reduction in gate oxide thickness. The amount and the impact of the band bending is accurately evaluated on a basis of one dimensional (1-D) self-consistent calculations including two-dimensional (2-D) subband structure of inversion-layer electrons and holes. It is demonstrated that additional band bending of a Si substrate due to C/sub inv/ becomes a dominant factor to limit the lowering of V/sub dd/ for CMOS with ultrathin gate oxides. The operation at V/sub dd/ lower than 0.6 V is quite difficult even with effective T/sub ox/ less than 1 nm.