Designing closer to the edge [deep submicron processes]

Summary form only given. Modern deep submicron CMOS processes cost /spl Theta/ or more to develop, qualify and deploy. Yet the incremental impact of each technology generation has been steadily decreasing due to a variety of phenomena such as increasing wire delay, power dissipation and reliability limits, and increasing process tolerances. We need to make better use of existing and future manufacturing processes in order to recoup our investment. It is often possible to obtain more performance out of an existing technology by better understanding of the process tolerances and trading off functional yield vs. performance. Given the above, it is clear that we need to understand and model design tolerances arising from processing variations. Until recently, it was sufficient to model such process-induced variations as intra-die shifts in device performance. However, in the deep submicron regime, within-die wire and device variations are comparable to die-to-die variations. This results in the need for new characterization, modeling and analysis techniques to handle these variations. In this work we expand on the ideas above, review the important trends in design uncertainty which directly drives design tolerance and hence performance. We review a number of research and applied approaches to design for manufacturability. The need to track process tolerances as a technology matures is stressed. This tracking is important since it acts as an information conduit between design and fabrication groups and enables designers to adapt the design to lower tolerances where possible.