A configurable 5-D packet classification engine with 4Mpacket/s throughput for high-speed data networking

Packet classification is critical in data networking. The object is to identify the highest priority rule that applies to an incoming packet. The rules are typically defined as arbitrary ranges over multiple fields of the packet header (e.g., destination/source address, dest/src port, etc.) and each rule specifies operations to be performed on a particular category of packets (assigning quality of service, route-pinning, firewall functions etc.). Matching algorithms implemented in software cannot keep up with ever-increasing data rates. Brute force comparison hardware is infeasible. To support 500 five-dimensional rules, at 4Mpackets/s throughput, 20B comparisons/s are needed. A processor is described which implements the proposed range-matching algorithm, exploiting the fact that N ranges can create at most 2N+1 non-overlapping intervals. For each such interval the rules that cover it are ordered by priority and stored in a bitmap array. The processor is realised in a 4-layer 0.25 /spl mu/m CMOS process and operates at a clock frequency of 66 MHz using a 3.3 V supply.