Impact of datapath unit for an efficient implementation of FFT processor

Fast Fourier transform (FFT) is always an accepted topic for research from past many years for different applications in the digital system. The computational unit of FFT consists butterfly units which have complex multiplication and complex addition. As multipliers are the basic computational element and also the slow and power consuming element in the processor special multipliers are used to overcome the downside. In this study, we have proposed a computationally efficient Fast Fourier Transform (FFT) based on radix-2 and radix-4 decimation in frequency algorithm, where different multipliers are carried out in FFT algorithm and parameters are compared. This entire work is performed on Xilinx ISE 14.7 and implemented on FPGA Xilinx vertex6 xc6vlx760-2ff1760.