New three dimensional (3D) memory array architecture for future ultra high density DRAM

A three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture's DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1 K-bit cells and the same design rules are used. Moreover, array area of 1 M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules.