Comprehensive Investigations on Degradations of Dynamic Characteristics for SiC Power MOSFETs Under Repetitive Avalanche Shocks

In this work, degradations of dynamic characteristics for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors under repetitive avalanche shocks are investigated in details. With the help of Silvaco TCAD simulations, gate capacitance versus gate voltage (C
_g
-V
_g
) measurement, and three-terminal charge pumping test, the main damaged position is demonstrated to be the SiC/SiO
₂
interface along junction FET (JFET) region instead of the body diode where most of the avalanche current passes through. Dominant avalanche degradation mechanism is then confirmed to be the injection of holes into the gate oxide above the JFET region. Since the channel region and the main junction of body diode are not seriously damaged by the avalanche stress, static parameters all remain stable. Meanwhile, due to the injection of holes, the depletion layer beneath the JFET region gets thinner, resulting in the increase of gate-drain capacitance (C
_gd
) under low drain-source voltage (V
_ds
) bias condition. It further takes responsibilities for the increments in input capacitance (C
_iss
), output capacitance (C
_oss
), and reverse transfer capacitance (C
_rss
). Moreover, it results in the extension of Miller plateau. Therefore, the increase of gate charge and delay of turn-off time after being stressed by repetitive avalanche shocks are monitored. Moreover, turn-on and turn-off dissipated energies after different unclamped-inductive-switching stress cycles are extracted. They are rarely influenced by the stress for the overlapping areas of voltage and current during switching procedures are relatively stable.