VLSI architectures for multidimensional transforms

The authors propose a family of VLSI architectures with area-time tradeoffs for computing (N*N* . . . *N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A=O(N/sup d+2a/) and computation time T=O(dN/sup d/2-a/b), and achieve the AT/sup 2/ bound of AT/sup 2/=O(n/sup 2/b/sup 2/) for constant d, where n=N/sup d/ and O>