Design guidelines for optimized nested Miller compensation

The nested Miller compensation of three-stage amplifiers is reviewed by using a novel and simple design-oriented approach allowing the control of the overall phase margin as well as that of each internal loop. Furthermore, a novel technique using nulling resistors to remove the RHP zeroes is discussed which greatly improves frequency and slew-rate performance, without increasing the power consumption. Thanks to the small compensation capacitors employed, the approach is suited for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.