Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

In this paper, the third quadrant behavior of a high-voltage superjunction mosfet (SJ-FET) in cascode configuration (CC) with a low-voltage silicon mosfet is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (tRR), reverse recovery peak current (IRRM), and reverse recovery charge (QRR). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used figure-of-merit RON·QRR, which considers the on-state resistance of the transistors (RON). In addition, the results obtained using an SJ-CC are similar or better than those achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the RON·QRR value provided by the SJ-CC is around eight times higher than that provided by a commercial GaN cascode.