Highly integrated 23 GHz receiver front-end chip

In this paper a very dense design of a complete 23 GHz front-end is presented-total chip measuring 1/spl times/1.5 mm, with an actual circuit area of only 840/spl times/1340 /spl mu/m. Performance compromises needed to achieve this level of integration are discussed and the resulting parameter deterioration is presented. Total conversion gain of the circuit is typically 22-23 dB and the noise figure is below 3.3 dB across most of the 22-24 GHz frequency range.